1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a semiconductor device having an internal circuit that operates in synchronization with an internal clock signal.
2. Description of the Background Art
FIG. 33 is a circuit block diagram representing an arrangement of a conventional semiconductor integrated circuit chip 71. In FIG. 33, semiconductor integrated circuit chip 71 includes a semiconductor substrate 72, a PLL (Phase Locked Loop) circuit 73 formed on a surface of semiconductor substrate 72, a clock buffer 74, and a plurality of (two in the diagram) logic circuits 75. PLL circuit 73 multiplies by a plural number a reference clock signal RCLK externally supplied via a clock terminal T to generate an internal clock signal intCLK. Internal clock signal intCLK is transmitted to a plurality of logic circuits 75 via clock buffer 74 and a clock line CL. Each logic circuit 75 performs a prescribed operation in synchronization with internal clock signal intCLK.
In the conventional semiconductor integrated circuit chip 71, however, internal clock signal intCLK having a frequency that is several-fold that of reference clock signal RCLK was supplied to each logic circuit 75 via clock buffer 74 and clock line CL so that there was a problem that the consumed power for charging and discharging clock line CL was too great.
When as many PLL circuits 73 as logic circuits 75 are provided, arranging each PLL circuit 73 in the vicinity of a corresponding logic circuit 75, and reference clock signal RCLK is supplied to each PLL circuit 73 via clock line CL, the consumed power of clock line CL becomes small since the frequency of reference clock signal RCLK is lower than the frequency of internal clock signal intCLK. The layout area would increase by the amount of the added PLL circuits 73, however.
Thus, the main object of the present invention is to provide a semiconductor device that requires small consumed power and small layout area.
A semiconductor device according to the present invention includes an internal circuit that operates in synchronization with an internal clock signal, a first delay circuit having a first delay time that is controlled by a control signal for delaying a reference clock signal, a second delay circuit having a second delay time that is controlled by the control signal and that is derived by multiplying the first delay time by a first proportionality constant for delaying the reference clock signal, a phase control circuit for comparing phases of the reference clock signal and an output clock signal from the first delay circuit to generate and supply to the first and second delay circuits the control signal such that a phase difference thereof becomes a predetermined value, and an internal clock generating circuit for generating and supplying to the internal circuit the internal clock signal obtained by multiplying the reference clock signal based on the reference clock signal and an output clock signal from the second delay circuit. Consequently, even in the case where a plurality of internal circuits exist, only one set of the first delay circuit and the phase control circuit needs to be provided for the multiple sets of the second delay circuit and the internal clock generating circuit so that reduction in the consumed power and in the layout area can be achieved.
Moreover, another semiconductor device according to the present invention includes an internal circuit that operates in synchronization with an internal clock signal, a frequency divider for dividing an external clock signal to generate a reference clock signal, a first delay circuit having a first delay time that is controlled by a control signal for delaying the external clock signal, a second delay circuit having a second delay time that is controlled by the control signal and that is derived by multiplying the first delay time by a predetermined proportionality constant for delaying the reference clock signal, a phase control circuit for comparing phases of the external clock signal and an output clock signal from the first delay circuit to generate and supply to the first and second delay circuits the control signal such that a phase difference thereof becomes a predetermined value, and an internal clock generating circuit for generating and supplying to the internal circuit the internal clock signal obtained by multiplying the reference clock signal based on the reference clock signal and an output clock signal from the second delay circuit. Consequently, even in the case where a plurality of internal circuits exist, only one set of the first delay circuit and the phase control circuit needs to be provided for multiple sets of the second delay circuit and the internal clock generating circuit so that reduction in the consumed power and in the layout area can be achieved. In addition, the first delay circuit delays the external clock signal so that the circuit scale of the first delay circuit can be kept small in comparison with the case where the reference clock signal generated in the frequency divider is delayed.
Moreover, a further semiconductor device according to the present invention includes an internal circuit that operates in synchronization with an internal clock signal, a ring oscillator for generating a first clock signal having a period controlled by a control signal, a delay circuit having a delay time that is controlled by the control signal and that is derived by multiplying the period of the first clock signal by a predetermined proportionality constant for delaying the first clock signal, a frequency divider for dividing the first clock signal to generate a second clock signal, a phase control circuit for comparing phases of a reference clock signal and the second clock signal and generating and supplying to the ring oscillator and the delay circuit the control signal such that a phase difference thereof becomes a predetermined value, and an internal clock generating circuit for generating and supplying to the internal circuit the internal clock signal that is obtained by multiplying the reference clock signal based on the first clock signal and an output clock signal from the delay circuit. Consequently, even when a plurality of internal circuits exist, only one set of the ring oscillator, the frequency divider, and the phase control circuit needs to be provided for multiple sets of the delay circuit and the internal clock generating circuit so that reduction in the consumed power and in the layout area can be achieved.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.